1. Field of the Invention
The present invention relates to a reset apparatus, and more particularly to a memory reset apparatus.
2. Description of Related Art
Generally, after a computer system is booted and each component in the computer system has been completely powered on, memories are required to be reset. FIGS. 1A and 1B are circuit diagrams of a conventional memory reset apparatus. Referring to FIG. 1A first, after a computer system is booted and each component in the computer system has been completely powered on, an indicating signal SPGD at a logical high voltage level is generated and transmitted to memories of different branches through a buffer 102, so as to ensure that the reset of the memories is performed after the computer system has been completely powered on.
Next, referring to FIG. 1B, a north bridge generates a reset signal SRESET at a logical high voltage level and generates a inverted reset signal SRESET—N (at a logical low voltage level) to memories of different branches through a transistor T1. When the indicating signal SPGD received by the memory of each branch is at a logical “high” voltage level and the inverted reset signal SRESET—N is at a logical “low” voltage level, the memories are reset. If the indicating signal SPGD and the inverted reset signal SRESET—N are at logical low voltage levels, the memories will not be reset.
Although the memory reset apparatus can complete resetting of the memories during booting the computer system, the conventional memory reset apparatus uses many circuit components, such that the wires are more congested when fabricating the layout diagram of the printed circuit board (PCB) and the circuit cost is thus increased.